Advances in Micro Electro Mechanical Systems (MEMS) technology have led to the development of devices and systems that have become ubiquitous in many markets, such as automotive, medical, consumer products, military hardware, and telecommunications. More recently, nanotechnology has begun to show promise in many of these and other areas as well.
MEMS and nanotechnology (broadly referred to as “microsystems technology”) derive from integrated-circuit (IC) fabrication processes that are directed toward the formation of mechanical structures on or in the surface of a substrate (typically a silicon or glass wafer). These structures form the bases of a variety of sensors and actuators. Devices such as pressure sensors, accelerometers, gyroscopes, displays, microphones, and optical switches have found commercial success due to the unique capabilities or properties afforded them by the exploitation of microsystems technology. In some cases, however, issues that arise from these fabrication processes themselves have hampered commercial exploitation of microsystems technology.
First, most microsystem fabrication is based on planar-fabrication processes such as layer deposition, photolithography, deep reactive-ion etching, and the like. Although such processes are useful for shaping objects in two-dimensions, they are not well suited to controllably sculpting a structure having a non-linear shape through its thickness.
Second, a microsystem is defined by its inclusion of at least one element that is free to move relative to the substrate on which it is formed (i.e., a mechanically active element). Typically, such an element is formed through a series of layer depositions and etches that leave it encased in a sacrificial material. To make the element mechanically active, the microsystem is subjected to an etch that selectively removes the sacrificial material thereby “releasing” the element from the substrate. Once released, however, mechanically active elements are susceptible to damage from incursion of foreign particles or fluids. As a result, released microsystems require special handling and care as compared to more conventional purely electronic integrated circuits.
A fully processed microsystem wafer ordinarily contains many chips (i.e., die), which are normally arranged in a regular pattern of rows and columns. Typically, before they can be packaged or included in a larger system, the chips must be separated from one another once fabrication is complete.
For conventional electronic integrated circuits, die singulation is a rather straightforward. An integrated-circuit wafer is protected with a layer of polymer or photoresist (normally spun on in liquid state and cured), and then indexed through a saw that cuts through the substrate material in allocated dicing lanes between the rows and columns of chips. During the sawing process, the substrate surface is irrigated with water to wash away debris and help keep the saw blade and substrate cool. After the sawing is complete, the protective layer is easily removed leaving the chips ready for packaging.
For microsystem wafers, however, die singulation is significantly more challenging. Their susceptibility to damage from foreign matter, such as particulates or liquids, means that released microsystem die must either be protected during die singulation or the mechanically active elements must be released after the chips have been separated.
Releasing individual die after singulation, however, is typically not commercially viable. Handling of individual die is cumbersome and negates much, if not all, of the cost advantage associated with batch fabrication and full-wafer processing. In addition, handling individual die is more difficult, which makes chip damage more likely. This not only inherently decreases product yield, but since such damage occurs to chips that are fully completed, the cost-of-scrap for the damaged chips is extremely high.
As a result, protecting microsystems die during singulation, wherein the microsystems have been released at the wafer level, is a more attractive approach. Several commercially successful approaches for separating microsystem chips have been developed in recent years. These are typically based on either providing a bonded cap over each microsystem chip or encapsulating each microsystem with a thin film.
Bonded cap approaches rely on one of several wafer-bonding techniques that can be performed at the wafer level. In such techniques, a cap wafer (typically glass or silicon) is joined to the microsystem wafer in regions surrounding each microsystem chip. These bonding regions must be reserved on the microsystem wafer specifically for this purpose. In some cases, cavities are formed in the cap layer to accommodate structure that projects above the microsystem-substrate surface. The cap wafer and microsystem wafer can be joined with any of several well-known wafer-bonding techniques. These include: high-temperature processes, such as fusion bonding, which is performed at temperatures of approximately 1000° C., or eutectic bonding, which is performed at temperatures in excess of 360° C.; thermo-anodic bonding, which is performed at temperatures typically within the range of approximately 300 to 500° C. while a voltage of several hundred volts is applied across the wafers; and “brazing-like” processes, wherein a bonding constituent, such as a polymer or solder, is provided between the wafers to substantially “glue” them together.
There are several drawbacks to these bonded-cap approaches, however. They add significant complexity to a fabrication process. Further, the addition of a second wafer, as well as the need to allocate space on the microsystem wafer for bonding, increases the overall cost of the resultant devices. In some cases, dissimilar materials, such as glass or metals, are used, which can introduce stress issues into the completed device. Many of these approaches rely upon elevated temperatures or the application of high voltage in order to achieve wafer bonding, which can create reliability issues. In addition, it can be difficult to individually encapsulate one or more small areas within the area of a microsystems chip.
Encapsulation of each microsystem die via a thin film comprises covering the microsystems with a sacrificial material and depositing a thin-film cap layer over the sacrificial layer. After access holes are formed through the cap layer, the sacrificial material is selectively removed and the access holes are sealed to form an enclosed chamber that surrounds the microsystem.
One thin-film encapsulation approach that has been used with great commercial success is referred to as the “epi-seal” process. In an epi-seal process, mechanically active elements formed in the active silicon layer of a silicon-on-insulator substrate are encased in a thin sacrificial layer of silicon dioxide. A first epitaxial layer of silicon is then deposited over the structures. Access holes are formed through this layer of silicon to expose the sacrificial silicon dioxide. After exposing the structures to a vapor-phase hydrofluoric acid treatment (which selectively etches the silicon dioxide), the devices are sealed via a second epitaxial silicon deposition, which closes the access holes thereby leaving the microsystem encapsulated. Epi-seal encapsulation has been shown to be robust enough to withstand the chip-dicing environment. In addition, it enables the final packaged device size to be comparable to the size of the microsystem itself. Further, the epi-seal process results in microsystems that are exclusively single-crystal silicon, which can result in performance advantages.
Epi-seal is not without its disadvantages, however. In many applications, for example, it is desirable to include other materials in addition to single-crystal silicon. Also, epitaxial growth of silicon requires relatively high deposition temperatures that preclude the use of many materials, such as polymers and some metals. Further, epi-seal limits the size of some device layer features, such as trenches, to 2 microns or less. This can restrain the range of motion for mechanically active elements in many designs.
Another thin-film encapsulation approach is based on the disposition of a layer comprising polymer membranes over each microsystem die. The polymer forms a seal that protects the microsystem from damage during dicing. After the chips are singulated, the polymer seals can be removed if desired.
Yet another alternative thin-film encapsulation approach relies upon deposition of a polymer or metallic thin-film layer over released areas of the microsystem chip to seal access through-holes used during the release process.
Although thin-film encapsulation avoids the need for a second wafer and allocated bonding area, it can increase the complexity of the fabrication. In addition, it is less flexible than the bonded-cap approach due to a limited number of appropriate sacrificial and cap layer materials. Further, it can be difficult to achieve suitable coverage over thick, wide structures. Still further, deposition-based encapsulation approaches can leave reactive gases and/or unintended material deposits within the encapsulated cavities. Finally, many such approaches involve additional handling steps and, therefore, inherently decrease production yield.